In many electronic components a semiconductor chip has to be mounted onto a carrier, in particular an electrically conductive carrier like, for example, a leadframe. It is important that the connection between the semiconductor chip and the carrier is of high reliability and exhibits high electrical and thermal conductivity. During and after the mounting process of the semiconductor chip onto the carrier, however, problems may occur depending on the applied fixation technology. The problems may arise, for example, from different thermal expansion coefficients of the semiconductor material and the carrier material which may lead to thermal mechanical stress. In case of thinned semiconductor chips these stress reactions may even lead to microscopic damage of the semiconductor chip like the formation of cracks. In other cases the stress may lead to a strong deformation of the semiconductor substrate so that the following process steps are no long possible like, for example, laser drilling, lamination, wire bonding, etc. In general the stress generated in the semiconductor chip severely affects the reliability of the following process steps. Therefore, there is a need for an interconnection technology which is able to provide a stable and permanently reliable connection between a semiconductor chip and a carrier with high electrical and thermal conductivity.